Asynchronous Transfer Mode (ATM) is a common way to format and transport data in a digital telecommunication system such as, for example, an Asymmetric Digital Subscriber Line (ADSL) link. ATM communicates data in streams of cells. An ATM cell comprises a five-byte cell header and 48 bytes of payload. The cell header contains address and control data, which is used in a network to direct the transfer of the ATM cell from its source to its destination. The payload contains the data to be communicated to the destination. FIG. 1 is a block diagram of an ATM cell 100. ATM cell 100 comprises a cell header 102 and a payload 104. Cell header 102 comprises four bytes of address and control data and one byte for a Header Error Control (HEC) value.
FIG. 2 is a block diagram of cell header 102. Note that in this figure, and purely for notational convenience, the bytes of the cell header are shown in right-to-left order compared with the left-to-right order in which they are shown in FIG. 1: the earliest-processed byte of the cell header 102 is the left-most byte in FIG. 1 but the right-most (least-significant) byte 252 in FIG. 2. Cell header 102 comprises a HEC byte 202 and address and control data bytes 204. From most to least significant bit, HEC byte 202 comprises a first bit 205, a second bit 206, a third bit 207, a fourth bit 208, a fifth bit 209, a sixth bit 210, a seventh bit 211, and an eighth bit 212. HEC byte 202 is used to validate the contents of address and control data bytes 204 against possible errors in transmission. The value of HEC byte 202 is defined as a complex function of the 32 bits of address and control data bytes 204. From most to least significant bit, address and control data bytes 204 comprise a first bit 213, a second bit 214, a third bit 215, a fourth bit 216, a fifth bit 217, a sixth bit 218, a seventh bit 219, an eighth bit 220, a ninth bit 221, a tenth bit 222, an eleventh bit 223, a twelfth bit 224, a thirteenth bit 225, a fourteenth bit 226, a fifteenth bit 227, a sixteenth bit 228, a seventeenth bit 229, an eighteenth bit 230, a nineteenth bit 231, a twentieth bit 232, a twenty-first bit 233, a twenty-second bit 234, a twenty-third bit 235, a twenty-fourth bit 236, a twenty-fifth bit 237, a twenty-sixth bit 238, a twenty-seventh bit 239, a twenty-eighth bit 240, a twenty-ninth bit 241, a thirtieth bit 242, a thirty-first bit 243, and a thirty-second bit 244. From most to least significant byte, address and control data bytes 204 comprise a first byte 246, a second byte 248, a third byte 250, and a fourth byte 252.
International standards for Digital Subscriber Line (DSL) systems (such as Recommendation ITU-T G992.1 entitled “Asymmetrical digital subscriber line (ADSL) transceivers,” Recommendation ITU-T G992.2 entitled “Splitterless asymmetric digital subscriber line (ADSL) transceivers,” Recommendation ITU-T G992.3 entitled “Asymmetric digital subscriber line transceivers—2 (ADSL2),” and Recommendation ITU-T G992.4 entitled “Splitterless asymmetric digital subscriber line transceivers 2 (splitterless ADSL2)”) define a method for conveying streams of ATM cells over a DSL link. Among other requirements, the method necessitates that when ATM cells 100 are communicated across the external data interface of a DSL modem, the bits in each byte of ATM cell 100 must be reversed in order. That is, whereas external to the DSL modem the most significant bit of each byte is processed first, within the DSL modem the least significant bit of each byte is processed first, and therefore the order of the bits within each byte must be reversed between external and internal forms so as to preserve the sequence in which the individual bits are processed, as the DSL standards require. This reversal applies to all bytes of ATM cell 100 including cell header 102.
Various standards for DSL also commonly require that when a DSL link is carrying ATM cells 100, the HEC byte 202 of each transmitted cell is generated according to the value of the address and control bytes of the cell header 102. They further commonly require that when an ATM cell 100 is received across a DSL link, its HEC byte 202 is checked for correctness in accordance to the values of the address and control bytes in the received cell header 102.
The process of generation of the HEC byte 202 for an ATM cell 100 according to the value of the address and control bytes is specified by various DSL standards to be performed in accordance with ITU-T Recommendation I.432 “B-ISDN user-network interface—Physical layer specification”, and to include the operation of combining the bit sequence ‘01010101’ into the sequence of eight HEC bits which comprise the basic HEC value, by addition modulo 2 (exclusive-or).
The process of checking validity of the HEC byte 202 for a received ATM cell 100 can be performed by generating a HEC byte value from the four bytes of address and control data within the received cell header 102, following the same process as is specified for HEC byte generation on transmission of an ATM cell 100, and comparing the generated HEC byte value for equality with the value of existing HEC byte 202 in the received cell header 102.
In an ATM-based modem in a telecommunication system, ATM cells 100 may be transmitted and received at a high rate. As identified above, it is commonly required that HEC byte 202 for each ATM cell 100 be generated by the modem upon transmission, and be checked for validity by the modem upon reception. Therefore, it is necessary to be able to generate the value of HEC byte 202 for each cell header 102 in an efficient manner. In older designs for modems, the streams of ATM cells 100 communicate though fixed-function hardware circuits that include logic circuits to compute or to check the value of HEC byte 202. However, in order to facilitate greater flexibility in modem development, it has become more common to use software to perform some modem functions. Unfortunately, computing the value of HEC byte 202 using software is a relatively complex process. Using conventional instructions (e.g., bit-wise shift, bit-wise exclusive-or, etc.), it may take many cycles to compute the value of HEC byte 202 for a single cell header 102. In a software-based multi-line modem, one processor may be required to handle several hundred thousand ATM cells 100 per second. Therefore, generation of the value of HEC byte 202 for each ATM cell 100 can represent a significant proportion of the total computational power of the modem. What is needed is a system or method that efficiently can generate the values of HEC bytes 202 for cell headers 102 for ATM cells 100.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.